RSX:
500 MHz G70 based GPU on 90 nm process, 300 milllion transistors 24 parallel pixel pipelines - 5 shader ALU operations per pipeline per cycle (2 vector4 and 2 scalar (dual/co-issue) and fog ALU)
- 27 FLOPS per pipeline per cycle 8 parallel vertex pipelines - 2 shader ALU operations per pipeline per cycle (1 vector4 and 1 scalar, dual issued)
- 10 FLOPS per pipeline per cycle 68 billion shader operations per second theoretical maximum ( ((5 ALU x 24 pixel pipelines) + (2 ALU x 8 vetrex pipelines)) x 500 MHz ) 364 GFLOPS ( ((27 FLOPS x 24 pixel pipelines) + (10 FLOPS x 8 vertex pipelines)) x 500 MHz )
Xenos:
500 MHz parent GPU on 90 nm TSMC process, 232 million transistors (337 million with 10MB eDram)
48-way parallel floating-point dynamically-scheduled shader pipelines
Unified shader architecture (each pipeline is capable of running either pixel or vertex shaders) - 2 shader ALU operations per pipeline per cycle (1 vector4 and 1 scalar, co-issued)
10 FLOPS per pipeline per cycle 48 billion shader operations per second theoretical maximum (2 ALU x 48 shader pipelines x 500 MHz) 240 GFLOPS (10 FLOPS x 48 shader pipelines x 500 MHz)