Intel
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Abu85 #7441 Intel Atom errata list:
1. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations
2. Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
3. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update
4. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
5. Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
6. BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer
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